AN415
EZRADIOPRO® PROGRAMMING GUIDE
1. Introduction
This document gives an overview of configuring the EZRadioPRO radios for transmitter, receiver, and transceiver operation via several simple software examples.
The following examples are covered in this programming guide:
How to use the EZRadioPRO transmitter or transceiver for packet transmission in FIFO mode
How to use the EZRadioPRO receiver or transceiver for packet reception in FIFO mode
How to use the EZRadioPRO transceiver for bidirectional packet-based communication
How to transmit and receive packets with longer than 64 bytes payload using the FIFO
The latest example source code is available on the Silicon Labs website: www.silabs.com/products/wireless/EZRadioPRO/ or on the WDS CDROM that ships with the evaluation board kits.
2. Hardware Options
The source code is provided for three EZRadioPRO transceiver chips: Si4431 Revision A0, Si4432 Revision V2, and Si443x Revision B1. There are few differences between the radios. The Si443x-B1 is the latest production revision. All the errata items of Si4431-A0 and Si4432-V2 are corrected on this silicon.
The Si4432-V2 requires some registers to be programmed to values other than their default values. These are not needed for the Si4431-A0.
The Si4431-A0 and Si443x-B1 have separate registers for setting the Auto-Frequency Calibration limit; however, the Frequency Deviation register is used for this purpose if the Si4432-V2 is used.
Different modem parameters have to be used for all revisions.
Invalid preamble timeout is defined differently for the Si4432-V2.
Separate source code examples are provided for all revisions with the differences highlighted in the programming guide.
Note: While only the Si4431-A0, Si4432-V2, and Si443x-B1 devices are mentioned in the document, the transmit or receive software works with the EZRadioPRO standalone transmitters and receivers.
The Si4431-A0 transmit example code works with the Si4031-A0 without any changes. The code is also applicable to the Si4430-A0 or Si4030A0, but the center frequency has to be set to the appropriate value.
The transmit example code provided for the Si4432-V2 works with the Si4032-V2 without any changes. The receive example code for the Si4431 works with the Si4330-A0 without any changes.
The Si443x-B1 transmit example code works with the Si403x-B1 without any changes. The code is also applicable to the Si4430-B1 and Si4030-B1, but the center frequency has to be set to the appropriate value.
The receiver example code for the Si443x-B1 works with the Si4330-B1 without any changes.
A separate Silicon Labs IDE workspace is provided for each example on the platforms. The name of the Silicon Labs IDE file shows the platform for which the given code is written:
Workspace filenames containing “SDBC_DK3” are written for the Software Development board.
Workspace filenames containing “EZLINK” are written for the EZLink platform.
Rev. 0.7 7/10 | Copyright © 2010 by Silicon Laboratories | AN415 |
AN415
2.1. Antenna Options
The power amplifier and the LNA are not connected to one another inside the EZRadioPRO devices. When using the Si4431 transceivers, the TX and RX pins can be directly connected externally, eliminating the need for an RF switch. When using the highest output power settings of the Si4432, separate transmit and receive pins on the RFIC are connected to an antenna via an SPDT RF switch. The EZRadioPRO devices assist with the control of the RF switches. By routing the RX State and TX State signals to any two GPIOs, the radio can automatically control the RF switch. The GPIOs control the RF switch to automatically connect the antenna to the receive path or transmit depending on the mode of operation. The GPIOs will disable the RF switch if the radio is not in active mode.
On the Single Antenna with RF Switch Testcard and on the EZLink SIL module, the same RF switch configuration is used: the TX State signal is routed to GPIO1 and the RX State signal is routed to GPIO2.
!" " #$% & | $# ' ( | ||||||||||||||||||||||||
B | A( | ||||||||||||||||||||||||
A0 | |||||||||||||||||||||||||
1 | B | ||||||||||||||||||||||||
, | |||||||||||||||||||||||||
A > | |||||||||||||||||||||||||
: | # | * | * | )' | > | ||||||||||||||||||||
A( | |||||||||||||||||||||||||
-- | =0 | ||||||||||||||||||||||||
9 | |||||||||||||||||||||||||
? | --*$# . * !$ | ||||||||||||||||||||||||
# | |||||||||||||||||||||||||
/ 0 ( 10 | |||||||||||||||||||||||||
# | |||||||||||||||||||||||||
)!$*!$&$+ , | |||||||||||||||||||||||||
( | @ | ||||||||||||||||||||||||
( | 3 1 | ||||||||||||||||||||||||
# | # | * | |||||||||||||||||||||||
( | |||||||||||||||||||||||||
8* | * | 1 | <![if ! IE]> <![endif]> 9 < 8 | 3A | <![if ! IE]> <![endif]>> | <![if ! IE]> <![endif]> | <![if ! IE]> <![endif]> | , | |||||||||||||||||
8# | 8# | <![if ! IE]> <![endif]>0 3 0 3 1 | <![if ! IE]> <![endif]>0 ? 0 | <![if ! IE]> <![endif]>0 0 | <![if ! IE]> <![endif]>0 ? | ||||||||||||||||||||
A | > | ||||||||||||||||||||||||
56 . " | 3 | , | |||||||||||||||||||||||
3A' | |||||||||||||||||||||||||
1 | 3A0 | A = | |||||||||||||||||||||||
3 | |||||||||||||||||||||||||
( | 1 | ||||||||||||||||||||||||
<![if ! IE]> <![endif]>=' A A = | |||||||||||||||||||||||||
<![if ! IE]> <![endif]>0 =' A =' A | 8 | ||||||||||||||||||||||||
9 # | A 0 | =0 | |||||||||||||||||||||||
8* | 1 | <![if ! IE]> <![endif]>' | 8 | ||||||||||||||||||||||
< | 9 | ||||||||||||||||||||||||
( | 1'= | # | |||||||||||||||||||||||
( | ( | <![if ! IE]> <![endif]>8 < 9 | <![if ! IE]> <![endif]>' | # | |||||||||||||||||||||
, | |||||||||||||||||||||||||
B | |||||||||||||||||||||||||
8 | |||||||||||||||||||||||||
* | * | ||||||||||||||||||||||||
; | 8 9* | * | < | 9 | |||||||||||||||||||||
=' | |||||||||||||||||||||||||
; | =0 | ||||||||||||||||||||||||
=' | |||||||||||||||||||||||||
8 | A( | ||||||||||||||||||||||||
< | 9 | A( | |||||||||||||||||||||||
A > | |||||||||||||||||||||||||
* | : | , | A0 | ||||||||||||||||||||||
2 3 3 /4$&5 6 $&5 #7 % ! ( | |||||||||||||||||||||||||
<![if ! IE]> <![endif]>=' | <![if ! IE]> <![endif]>=' | <![if ! IE]> <![endif]>=' | 8 | ||||||||||||||||||||||
<![if ! IE]> <![endif]>; | < | 9 | |||||||||||||||||||||||
<![if ! IE]> <![endif]>;9 | |||||||||||||||||||||||||
<![if ! IE]> <![endif]>;< | |||||||||||||||||||||||||
* | |||||||||||||||||||||||||
<![if ! IE]> <![endif]>; | , | ||||||||||||||||||||||||
<![if ! IE]> <![endif]> | R | ||||||||||||||||||||||||
SILICON LABORATORIES | |||||||||||||||||||||||||
<![if ! IE]> <![endif]>? | <![if ! IE]> <![endif]>(? | <![if ! IE]> <![endif]><89 | |||||||||||||||||||||||
SILICON LABS | |||||||||||||||||||||||||
<![if ! IE]> <![endif]> | |||||||||||||||||||||||||
' | |||||||||||||||||||||||||
Figure 1. Single Antenna with RF Switch Si4432 Testcard Schematic
If the Si4431-B1 device is used, it is possible to tie together the receive and transmit paths on the PCB directly. It is not necessary to control the RF switch; therefore, all the GPIOs can be used for any other feature.
2 | Rev. 0.7 |
AN415 | |||||||||||||||||||||||||||
!" " #$% & | $# ' ( | ||||||||||||||||||||||||||
B | A( | ||||||||||||||||||||||||||
A0 | |||||||||||||||||||||||||||
1 | B | ||||||||||||||||||||||||||
9 | |||||||||||||||||||||||||||
, | < | A > | |||||||||||||||||||||||||
: | # | * | * | )' | > | 8 | |||||||||||||||||||||
-- | A( | ||||||||||||||||||||||||||
=0 | |||||||||||||||||||||||||||
9 | |||||||||||||||||||||||||||
56 . " | ? | --*$# . * !$ | |||||||||||||||||||||||||
# | |||||||||||||||||||||||||||
# | / 0 ( 10 | ||||||||||||||||||||||||||
3 | ( | ( | @ | )!$*!$&$+ , | |||||||||||||||||||||||
( | 3 1 | ||||||||||||||||||||||||||
# | # | ||||||||||||||||||||||||||
89* | * | ||||||||||||||||||||||||||
( | ( | ( | ( | ||||||||||||||||||||||||
* | <* | 1 | <![if ! IE]> <![endif]> 9 < 8 | 3A | <![if ! IE]> <![endif]>> | <![if ! IE]> <![endif]> | <![if ! IE]> <![endif]> | , | |||||||||||||||||||
<![if ! IE]> <![endif]>0 3 0 3 1 0 ? 0 | <![if ! IE]> <![endif]>0 0 | <![if ! IE]> <![endif]>0 ? | |||||||||||||||||||||||||
* | A | > | |||||||||||||||||||||||||
3 | , | ||||||||||||||||||||||||||
3A' | |||||||||||||||||||||||||||
3A0 | A = | ||||||||||||||||||||||||||
<![if ! IE]> <![endif]>=' A =' A =' A A = | |||||||||||||||||||||||||||
8 | |||||||||||||||||||||||||||
<![if ! IE]> <![endif]>0 | |||||||||||||||||||||||||||
# | # | <![if ! IE]> <![endif]>' | 8 | ||||||||||||||||||||||||
< | 9 | ||||||||||||||||||||||||||
<![if ! IE]> <![endif]>8 < 9 | <![if ! IE]> <![endif]>' | # | , | ||||||||||||||||||||||||
B | |||||||||||||||||||||||||||
8 | |||||||||||||||||||||||||||
< | 9 | ||||||||||||||||||||||||||
=0 | |||||||||||||||||||||||||||
* | |||||||||||||||||||||||||||
8 | A( | ||||||||||||||||||||||||||
< | 9 | A( | |||||||||||||||||||||||||
A > | |||||||||||||||||||||||||||
* | : | , | A0 | ||||||||||||||||||||||||
2 " ! &$ $6 | $&5 #7 % ! 989( | ||||||||||||||||||||||||||
<![if ! IE]> <![endif]>=' | <![if ! IE]> <![endif]>=' | <![if ! IE]> <![endif]>=' | 8 | ||||||||||||||||||||||||
<![if ! IE]> <![endif]>; | < | 9 | |||||||||||||||||||||||||
<![if ! IE]> <![endif]>;9 | |||||||||||||||||||||||||||
<![if ! IE]> <![endif]>;< | |||||||||||||||||||||||||||
, | * | ||||||||||||||||||||||||||
<![if ! IE]> <![endif]>; | |||||||||||||||||||||||||||
<![if ! IE]> <![endif]> | R | ||||||||||||||||||||||||||
SILICON LABORATORIES | |||||||||||||||||||||||||||
<![if ! IE]> <![endif]>? | <![if ! IE]> <![endif]>(? | <![if ! IE]> <![endif]><89, | |||||||||||||||||||||||||
SILICON LABS | |||||||||||||||||||||||||||
<![if ! IE]> <![endif]> | |||||||||||||||||||||||||||
989 | |||||||||||||||||||||||||||
' | |||||||||||||||||||||||||||
Figure 2. Direct Tie Si4431 Testcard Schematic
One of the key advantages of the EZRadioPRO devices is the built-in antenna diversity support in which two different polarization antennas are connected to the radio. At the beginning of the packet reception, the chip evaluates the received signal strength level for both antennas and uses the better one to receive the remainder of the data packet. By selecting the strongest antenna, receiver performance in the presence of multipath fading and changing antenna polarization can be greatly improved.
When using this feature, an RF switch is needed to connect the antennas to the receive or transmit path. EZRadioPRO devices control the RF switch automatically through any two GPIOs. By routing the Antenna1 Switch used for antenna diversity and the Antenna2 Switch used for antenna diversity signals to the GPIOs, the radio automatically switches between antennas during receive mode. The antenna used for reception of the RX packet is used for the subsequent TX packet transmission. On the Antenna Diversity Testcard, GPIO1 is routed to the Antenna1 Switch used for antenna diversity signals, and GPIO2 is routed to the Antenna2 Switch used for antenna diversity signals for controlling the RF switch.
Rev. 0.7 | 3 |
AN415
!" " #$% & $# ' (
: | # | * | * | - | |||||||
- | |||||||||||
( | |||||||||||
- | - | - | |||||||||
( | |||||||||||
( | |||||||||||
- | - | ||||||||||
- | - | - | - | ||||||||
( | ( | ||||||||||
( | |||||||||||
<![if ! IE]> <![endif]>8 | 1'= 8 0 | ||||||||||
- | - | <![if ! IE]> <![endif]>0 3 | |||||||||
1 | |||||||||||
=0 < | |||||||||||
<![if ! IE]> <![endif]>0 3 | |||||||||||
<![if ! IE]> <![endif]> | |||||||||||
( | - | ||||||||||
- | - | ||||||||||
( | ( | ( | ; | - | |||||||
=' | |||||||||||
- | - | ; | |||||||||
=' |
-'. / % #" $5 & 6* # #$ 2 .: / # $5 $ D. D . 4E
4432-T-B1 A
Freq. | RX Side | TX side | |||||||||||||||||||
band | LR | CR1 | CR2 | L1 | R3 | C0 | LH | CH | RH | L0 | CM | LM | CC1, CC2, CC3 | CM2, CM4 | LM2,LM3 | CM3, CM5 | |||||
[MHz] | [nH] | [pF] | [pF] | [nH] | [Ohm] | [pF] | [nH] | [pF] | [Ohm] | [nH] | [pF] | [nH] | [pF] | [pF] | [nH] | [pF] | |||||
315 | 47 | 5.6 | 15 | 390 | 150 | 18 | 15 | 50 | 33 | 10 | 33 | 390 | 15 | 24 | 15 | ||||||
434 | 33 | 4.7 | 10 | 270 | 120 | 11 | 12 | 50 | 24 | 6.8 | 24 | 270 | 8.2 | 18 | 8.2 | ||||||
470 | 27 | 4.7 | 12 | 270 | 100 | 10 | 11 | 50 | 22 | 5.6 | 22 | 220 | 9.1 | 15 | 9.1 | ||||||
868 | 11 | 3.9 | 6.8 | 120 | 39 | 5.6 | 6.0 | 50 | 15 | 3.3 | 15 | 68 | 4.7 | 9.1 | 4.7 | ||||||
915 | 11 | 3.3 | 6.8 | 120 | 33 | 5.6 | 5.6 | 50 | 12 | 3.0 | 12 | 56 | 4.3 | 8.2 | 4.3 |
B | A( | ||||||||||||||||
A0 | |||||||||||||||||
1 | B | ||||||||||||||||
9 | |||||||||||||||||
, | < | ||||||||||||||||
)' | > | 8 | A > | ||||||||||||||
-- | =0 | A( | |||||||||||||||
9 | |||||||||||||||||
? | --*$# . * !$ | ||||||||||||||||
# | |||||||||||||||||
/ 0 ( 10 | |||||||||||||||||
@ | )!$*!$&$+ , | ||||||||||||||||
( | 3 1 | ||||||||||||||||
1 | <![if ! IE]> <![endif]> 9 < 8 | 3A | <![if ! IE]> <![endif]>> | <![if ! IE]> <![endif]> | <![if ! IE]> <![endif]> | , | |||||||||||
<![if ! IE]> <![endif]>0 | <![if ! IE]> <![endif]>3 0 3 1 0 ? 0 | <![if ! IE]> <![endif]>0 0 | <![if ! IE]> <![endif]>0 ? | ||||||||||||||
A | > | ||||||||||||||||
3 | , | ||||||||||||||||
3A' | |||||||||||||||||
3A0 | A = | ||||||||||||||||
<![if ! IE]> <![endif]>=' A =' A =' A A = | |||||||||||||||||
<![if ! IE]> <![endif]>0 | <![if ! IE]> <![endif]>' | 8 | |||||||||||||||
8 | |||||||||||||||||
< | 9 | ||||||||||||||||
<![if ! IE]> <![endif]>8 < 9 | <![if ! IE]> <![endif]>' | # | , | ||||||||||||||
B | |||||||||||||||||
8 | |||||||||||||||||
- | < | 9 | |||||||||||||||
=0 | |||||||||||||||||
8 | A( | ||||||||||||||||
< | 9 | A( | |||||||||||||||
A > | |||||||||||||||||
* | : | , | A0 | ||||||||||||||
<![if ! IE]> <![endif]>=' | <![if ! IE]> <![endif]>=' | <![if ! IE]> <![endif]>=' | <![if ! IE]> <![endif]>; | <![if ! IE]> <![endif]>;9 | <![if ! IE]> <![endif]>;< | 8 | |||||||||||
< | 9 | ||||||||||||||||
<![if ! IE]> <![endif]>; | * | ||||||||||||||||
, | |||||||||||||||||
<![if ! IE]> <![endif]> | R | ||||||||||||||||
<![if ! IE]> <![endif]>? | <![if ! IE]> <![endif]>(? | <![if ! IE]> <![endif]><89 | SILICON LABORATORIES | ||||||||||||||
SILICON LABS | |||||||||||||||||
C | |||||||||||||||||
' | < | ||||||||||||||||
Figure 3. Antenna Diversity Si4432 Testcard Schematic
The example source code for the Software Development board can be compiled for various Testcards. The following compiling options, located at the beginning of the main_sdbc_dk3.c file, select the proper configuration for the different testcards:
TX/RX Split or Direct Tie Antenna configuration | #define SEPARATE_RX_TX | ||
| Single Antenna with RF switch | #define | ONE_SMA_WITH_RF_SWITCH |
| Antenna Diversity | #define | ANTENNA_DIVERSITY |
There is no compiling option in the source code of the EZLink platform since it is a fixed hardware configuration. From a radio functionality point of view, it is equivalent to a Single Antenna with RF Switch testcard.
Note: The transmit output of the EZRadioPRO devices has to be terminated properly before output power is enabled. This is accomplished by using a proper antenna or connecting the power amplifier to an RF instrument that provides 50 termination to ensure proper operation and protect the device from damage.
4 | Rev. 0.7 |
AN415
2.2. Initializing the MCU
The software examples use a minimal set of the microcontroller’s available hardware peripherals to minimize the complexity of the source code. The following hardware support is provided:
Packet transmission is initiated by pressing a button.
Packet transmission and packet reception are indicated via LED.
The EZRadioPRO devices are connected via SPI to the MCU with the nIRQ pin of the radio connected to an external interrupt pin of the MCU.
While the SPI and nIRQ connections between the EZRadioPRO device and the MCU are the same on both hardware platforms, there are some differences in the peripherals:
The example source code uses only the push button(s) and LED(s) on both platforms; however, the Software Development board has four LEDs and four push buttons, while the EZLink has only one of each. The LEDs and push buttons are on different IO pins on the two platforms.
The PWRDN pin of the radio is connected to the MCU on the EZLink platform; so, the MCU can use it to control the radio. This connection is not available on the Software Development board, and the PWRDN pin is connected to the GND.
2.2.1. Initialization of the Software Development Board
The MCU-dependent header files are included in the source code to provide the macro definitions allowing the code to be compiled with several common C compilers (like Keil, SDCC, IAR, etc.).
/* ======================================================== * * INCLUDE *
* ======================================================== */ #include "C8051F930_defs.h"
#include "compiler_defs.h"
/* ================================================================ *
* C8051F930 Pin definitions for Software Development Board | * | ||
* | (using compiler_def.h macros) | * |
* ================================================================ */
The following macros assign a label to the given IO port; so, they can be more easily referenced in the source code. For example, the first line assigns the “NSS” label to Port1.3 where the nSEL pin of the radio is connected:
SBIT(NSS, SFR_P1, 3);
SBIT(NIRQ, SFR_P0, 6);
SBIT(PB1, SFR_P0, 0);
SBIT(PB2, SFR_P0, 1);
SBIT(PB3, SFR_P2, 0);
SBIT(PB4, SFR_P2, 1);
SBIT(LED1, SFR_P1, 4);
SBIT(LED2, SFR_P1, 5);
SBIT(LED3, SFR_P1, 6);
SBIT(LED4, SFR_P1, 7);
The following definitions are used to configure the type of testcard plugged into the Software Development board.
//One out of these definitions has to be uncommented which tells to the compiler what kind //of Testcard is plugged into the Software Development board
#define SEPARATE_RX_TX //#define ANTENNA_DIVERSITY
//#define ONE_SMA_WITH_RF_SWITCH
Rev. 0.7 | 5 |
AN415
Following are the function prototypes for MCU initialization and SPI functions.
/* ======================================================== * * Function PROTOTYPES *
* ======================================================== */ //MCU initialization
void MCU_Init(void); //SPI functions
void SpiWriteRegister (U8, U8); U8 SpiReadRegister (U8);
The void MCU_Init(void) function initializes all the necessary peripherals for the Software Development board:
void MCU_Init(void)
{
//Disable the Watch Dog timer of the MCU PCA0MD &= ~0x40;
// Set the clock source of the MCU: 10MHz, using the internal RC osc. CLKSEL = 0x14;
// Initialize the IO ports and the cross bar
P0SKIP |= 0xCF; | // skip P0.0-3 & 0.6-7 | |
XBR1 | |= 0x40; | // Enable SPI1 (3 wire mode) |
P1MDOUT |= 0x01; | // Enable SCK push pull | |
P1MDOUT |= 0x04; | // Enable MOSI push pull | |
P1SKIP |= 0x08; | // skip NSS | |
P1MDOUT |= 0x08; | // Enable NSS push pull | |
P1SKIP |= 0xF0; | // skip LEDs | |
P1MDOUT |= 0xF0; | // Enable LEDS push pull | |
P2SKIP |= 0x03; | // skip PB3 & 4 | |
SFRPAGE = CONFIG_PAGE; | ||
P1DRV | = 0xFD; | // MOSI, SCK, NSS, LEDs high current mode |
SFRPAGE = LEGACY_PAGE; | ||
XBR2 | |= 0x40; | // enable Crossbar |
// For the SPI communication the hardware peripheral of the MCU is used //in 3 wires Single Master Mode. The select pin of the radio is controlled //from software
SPI1CFG | = 0x40; | //Master SPI, CKPHA=0, CKPOL=0 |
SPI1CN | = 0x00; | //3-wire Single Master, SPI enabled |
SPI1CKR | = 0x00; | |
SPI1EN = 1; | // Enable SPI interrupt | |
NSS = 1; | ||
// Turn off the LEDs | ||
LED1 = 0; | ||
LED2 = 0; | ||
LED3 = 0; | ||
LED4 = 0; | ||
} | ||
6 | Rev. 0.7 |
AN415
The void SpiWriteRegister(U8 reg, U8 value) function writes a new value into a register on the radio. If only one register of the radio is written, a 16-bit value must be sent to the radio (the 8-bit address of the register followed by the new 8-bit value of the register). To write a register, the MSB of the address is set to 1 to indicate a device write.
void SpiWriteRegister (U8 reg, U8 value)
{
// Send SPI data using double buffered write
//Select the radio by pulling the nSEL pin to low NSS = 0;
//write the address of the register into the SPI buffer of the MCU
//(important to set the MSB bit) | |
SPI1DAT = (reg|0x80); | //write data into the SPI register |
//wait until the MCU finishes sending the byte while( SPIF1 == 0);
SPIF1 = 0;
//write the new value of the radio register into the SPI buffer of the MCU
SPI1DAT = value; | //write data into the SPI register |
//wait until the MCU finishes sending the byte | |
while( SPIF1 == 0); | //wait for sending the data |
SPIF1 = 0; |
//Deselect the radio by pulling high the nSEL pin NSS = 1;
}
The U8 SpiReadRegister(U8 reg) function reads one register from the radio. When reading a single register of the radio, a 16 bit value must be sent to the radio (the 8-bit address of the register followed by a dummy 8-bit value). The radio provides the value of the register during the second byte of the SPI transaction. Note that it is crucial to clear the MSB of the register address to indicate a read cycle.
U8 SpiReadRegister (U8 reg)
{
//Select the radio by pulling the nSEL pin to low NSS = 0;
//Write the address of the register into the SPI buffer of the MCU //(important to clear the MSB bit)
SPI1DAT = reg; //write data into the SPI register //Wait until the MCU finishes sending the byte
while( SPIF1 == 0); SPIF1 = 0;
//Write a dummy data byte into the SPI buffer of the MCU. During sending //this byte the MCU will read the value of the radio register and save it
//in its SPI buffer. | |
SPI1DAT = 0xFF; | //write dummy data into the SPI register |
//Wait until the MCU finishes sending the byte while( SPIF1 == 0);
SPIF1 = 0;
//Deselect the radio by pulling high the nSEL pin NSS = 1;
//Read the received radio register value and return with it return SPI1DAT;
}
Rev. 0.7 | 7 |
AN415
2.2.2. Initialization of the EZLink Platform
The initialization of the EZLink platform is very similar to the Software Development board and differs only in the control of the EZRadioPRO PWRDN pin. By driving this pin high, the radio is completely switched off allowing for minimal power consumption, but the values of the registers are not kept. Driving this pin low enables the radio and performs a power on reset cycle, which takes about 15 ms. The radio is not ready to receive any SPI commands in power down mode or during the power on reset cycle. That is the reason for a delay in the main function after the MCU is initialized and the PWRDN pin of the radio is driven low.
//Initialize the MCU:
//- set IO ports for the Software Development board
//- set MCU clock source
//- initialize the SPI port
//- turn off LEDs
MCU_Init();
/* ======================================================== * * Initialize the Si4432 ISM chip *
* ======================================================== */ //Turn on the radio by pulling down the PWRDN pin
SDN = 0;
//Wait at least 15ms before any initialization SPI commands are sent to the radio // (wait for the power on reset sequence)
for (temp8=0;temp8<15;temp8++)
{
for(delay=0;delay<10000;delay++);
}
//read interrupt status registers to clear the interrupt flags and release NIRQ pin
ItStatus1 = SpiReadRegister(0x03); | //read the Interrupt Status1 register |
ItStatus2 = SpiReadRegister(0x04); | //read the Interrupt Status2 register |
8 | Rev. 0.7 |
AN415
3. Packet Transmission Using the Transmit Packet Handler
This software example uses push buttons on the hardware platform to initiate a packet transmission. After power on reset, the firmware initializes the MCU and the EZRadioPRO chip. The chip is set to IDLE mode, where only the crystal oscillator of the radio is running, and the software waits for a button press. If any of the push buttons are pressed on the Software Development board, the demo sends a packet then returns to polling the push buttons. The packet configuration used for the transmission is as shown in Table 1.
Table 1. Demo Code Packet Configuration
Preamble | Synchron | Payload | Payload: “Button1+CR” | CRC | ||||||||||||||||
pattern | length | |||||||||||||||||||
55 | 55 | 55 | 55 | 55 | 2D | D4 | 08 | 42 | 75 | 74 | 74 | 6F | 6E | 31 | 0D | 7A | B1 | |||
5 bytes | 2 bytes | 1 byte | 8 bytes | 2 bytes |
(10 bytes if Ant. Diversity is used)
The payload of the packet is set according to the push button pressed.
Note: Since there is only one push button on the EZLink platform, it always sends the “Button1” payload.
While the only real application information in the packet is the string that tells which button is pressed, the actual packet requires several additional bytes around the payload for proper operation. These additional packet fields include a preamble, sync word, payload length, and CRC.
After enabling the receiver on the radio, it will start to receive data even if there is no signal present. In order for the receiver to detect that a valid packet is present, the transmitted packet should start with a preamble and a synchron pattern.
The preamble is a continuous 0101 sequence used to synchronize the transmitter and receiver. The preamble is a known sequence with continuous edge changes in the data so that the demodulator and clock recovery circuit of the receiver node can be settled correctly. The minimum required preamble length is applicationdependent. See "4. Packet Receiving Using the Receive Packet Handler" on page 18 for more details.
After the transmitter and receiver have synchronized, the receiver has to find out where the payload data in the packet starts. The transmitter includes a known bit pattern to help identify the payload data, the synchron word.
The receiver also needs to know how long the transmitted packet is. There are several possibilities that can be used to indicate the length of the packet:
Send a special end character at the end of the packet.
Always transmit a fixed length packet.
Include the length information in the transmitted packet.
In the example code, the length of the payload is included in the packet.
In the RF physical channel, the transmitted packet can become corrupted by noise or another RF transmitter can send a packet at the same instant; so, it is strongly recommended that some kind of error checking be used to confirm whether the received data is valid or contains errors.
If the communication is disturbed, it can cause a burst of bit errors, which can be identified by using a CRC. While a simple checksum can be used to recognize single-bit errors, most link disruptions result in burst errors, which require the CRC for robust detection.
Rev. 0.7 | 9 |
AN415
3.1. Initialization of the Radio
The EZRadioPRO radio has a built-in packet handler for automatic packet transmission and reception. Once the basic packet parameters are initialized, only the payload data needs to be sent to the onboard FIFO of the radio, and packet transmission will automatically start. The entire packet is built up and sent by the radio without the use of the microcontroller. When the packet transmission is finished, the radio generates an interrupt for the microcontroller and goes back to the previously-active state.
This section describes how the EZRadioPRO transmitter or transceiver devices can be configured to send the packet shown in Table 1. The tx_SDBC_DK3 or tx_EZlink example projects are used to demonstrate packet transmission. The code segments used in this chapter are copied from the main_sdbc_dk3.c or main_ezlink.c files.
The code section for initialization the radio must be performed in case of the following:
A reset event occurs.
The power-down pin of the radio is pulled low (radio enabled).
Note: The power-on reset cycle of the EZRadioPRO devices takes about 15 ms. During this reset period, the radios cannot accept any SPI command. There are two ways to determine if the chip is ready to receive SPI commands after a reset event:
Use a timer in the microcontroller to wait for 15 ms.
Enable the external interrupt of the microcontroller and wait for an interrupt from the radio. In the MCU ISR routine, check the “ipor” interrupt status bit, which will be set if the POR event finished correctly.
3.1.1. Software Reset for the Radio
If the microcontroller handles the power-on reset for the entire application, it is recommended that a software reset be provided for the radio every time the microcontroller performs a power-on reset sequence.
The following code section shows how to perform a software reset for the radio and determine when the reset procedure is finished, allowing the radio to receive SPI commands from the microcontroller:
//SW reset | |
SpiWriteRegister(0x07, 0x80); | //write 0x80 to the Operating & Function Control1 register |
//wait for chip ready interrupt from the radio (while the nIRQ pin is high) while ( NIRQ == 1);
//read interrupt status registers to clear the interrupt flags and release NIRQ pin
ItStatus1 = SpiReadRegister(0x03); | //read the Interrupt Status1 register |
ItStatus2 = SpiReadRegister(0x04); | //read the Interrupt Status2 register |
3.1.2. Set RF Parameters
The following section sets the basic RF parameters needed to do OOK, FSK, or GFSK modulated packet transmission. These parameters include center frequency, transmit data rate, and transmit deviation.
/*set the physical parameters*/ //set the center frequency to 915 MHz
SpiWriteRegister(0x75, 0x75); //write 0x75 to the Frequency Band Select register SpiWriteRegister(0x76, 0xBB); //write 0xBB to the Nominal Carrier Frequency1 register SpiWriteRegister(0x77, 0x80); //write 0x80 to the Nominal Carrier Frequency0 register
//set the desired TX data rate (9.6kbps)
SpiWriteRegister(0x6E, 0x4E); | //write 0x4E to the TXDataRate 1 register |
SpiWriteRegister(0x6F, 0xA5); | //write 0xA5 to the TXDataRate 0 register |
SpiWriteRegister(0x70, 0x2C); | //write 0x2C to the Modulation Mode Control 1 register |
//set the desired TX deviation (+-45 kHz)
10 | Rev. 0.7 |
AN415
SpiWriteRegister(0x72, 0x48); //write 0x48 to the Frequency Deviation register
Note: For OOK modulation, there is no need to configure the transmit deviation.
Besides the TX Data Rate 0 and TX Data Rate 1 registers, an additional bit is used to define the data rate: “txdtrtscale” (bit5 in the Modulation Mode Control1 register). The “txdtrtscale” bit must be set to 1 if the desired data rate is below 30 kbps.
The MSB of the deviation setting can be found in the Modulation Mode Control register 2 (fd[8] – bit2).
3.1.3. Set Packet Configuration
The EZRadioPRO devices provide a flexible packet handler that can support a wide range of packet configurations including the following:
Programmable preamble (up to 255 bytes)
Programmable synchronization word length and pattern (up to four bytes)
Automatic header generation and qualification (up to four bytes)
Fixed and variable length packets
Payload data of up to 64 bytes (using the built-in FIFO)
Automatic CRC calculation and verification (with support for three different CRC polynomials)
If the user’s application operates with a packet configuration conforming to the above options, the EZRadioPRO packet handler can be used. Using the packet handler allows the MCU to configure the transmit packet format and structure during configuration. When a packet is transmitted, the MCU only needs to place the payload data into the TX FIFO before each packet transmission and the packet handler will automatically construct and transmit the packet.
Note: If the user's application operates with a packet configuration that is not supported by the packet handler, the EZRadioPRO devices can be operated in the following modes as well:
Direct mode or Synchronous Direct mode (check the EZRadioPRO data sheet for more details).
RAW data mode (See “AN463: RAW Data Mode with EZRadioPRO®” for more details).
Another powerful feature of the EZRadioPRO devices is Automatic Antenna Diversity. Antenna diversity allows the receiver to use two separate antennas to help combat multi-path fading or antenna polarization effects. The receiver will automatically evaluate the signal strength on both antennas and select the antenna with maximum power. While antenna diversity is used during receiving mode, the transmitter needs to be properly configured for the system to support diversity. The following considerations need to be followed for antenna diversity operation:
A longer preamble is required to allow the receiver to evaluate the signal strength level on both antennas to determine which is optimal for receiving the packet.
The built-in antenna diversity algorithm uses the GPIO pins to control the RF switch (for selecting the proper antenna). Two GPIOs must be configured to route the control signals for the RF switch.
The proper signal polarity of the RF switch control signal must be configured.
The example code shown below demonstrates how to configure the packet handler for the sample packet shown in Table 1.
The example can be compiled for Antenna Diversity or non-Antenna diversity operation. The selection is made via the following configuration options as described in "2. Hardware Options" on page 1: SEPARATE_RX_TX, ANTENNA_DIVERSITY, and ONE_SMA_WITH_RF_SWITCH.
The preamble length is set depending on whether the antenna diversity algorithm is enabled:
When antenna diversity is disabled, a 5 byte preamble is transmitted. The shorter preamble allows the receiver to enable auto-frequency calibration (AFC) with a preamble detection threshold of two bytes. (Receiver configuration is described in more detail in "4. Packet Receiving Using the Receive Packet Handler" on page 18.)
When antenna diversity is enabled, a longer preamble must be transmitted. The longer preamble allows additional time for the receiver to evaluate the signal strength for both antennas, settle the clock recovery circuit correctly, etc.
Rev. 0.7 | 11 |
AN415
/*set the packet structure and the modulation type*/
//set the preamble length to 10bytes if the antenna diversity is used and set to 5bytes if not #ifdef ANTENNA_DIVERSITY
SpiWriteRegister(0x34, 0x14); //write 0x14 to the Preamble Length register
#else
SpiWriteRegister(0x34, 0x09); //write 0x09 to the Preamble Length register
#endif
Disable the header bytes (not used in this example) and set the synchron word length to two bytes.
Note: The MSB bit of the preamble length setting is located in this register (“prealen8”—bit0 in the Header Control2 register).
//Disable header bytes; set variable packet length (the length of the payload is defined by the //received packet length field of the packet); set the synch word to two bytes long SpiWriteRegister(0x33, 0x02); //write 0x02 to the Header Control2 register
Set the synchron word pattern for 0x2DD4. At least two bytes of synchron word are recommended to increase the robustness of the communication. The synchron word pattern is a system-level design consideration. For interoperability with EZRadio devices, the synchron word must be set to 0x2DD4. The synchron word can also be used as a packet filter by using different values for different applications or node types. Different synchron word vales can be used by the receiver to filter and receive only communication from the desired node.
//Set the sync word pattern to 0x2DD4
SpiWriteRegister(0x36, 0x2D); | //write 0x2D to the Sync Word 3 register |
SpiWriteRegister(0x37, 0xD4); | //write 0xD4 to the Sync Word 2 register |
Enable the TX packet handler and the CRC16 calculation:
//enable the TX packet handler and CRC-16 (IBM) check
SpiWriteRegister(0x30, 0x0D); //write 0x0D to the Data Access Control register
This example will use the EZRadioPRO 64-byte TX FIFO to provide the data for the TX packets. By using the FIFO, the MCU simply provides the data to fill the FIFO; the radio generates the correct bit timing internally and modulates the output signal. The FIFO can be used with the TX packet handler to construct the packet format, or the entire packet can be calculated in the MCU and placed into the TX FIFO.
When the TX packet handler is not used, no packet forming is provided by the radio. The MCU should construct the entire packet (including preamble, synchron word, header fields, payload, etc.) and fill the formed packet into the transmit FIFO.
EZRadioPRO also supports several modes to provide the packet data as data bits to the radio:
Using one of the GPIOs for direct modulation
In this case the MCU has to form the packet and provide the data bits with the right bit timing to the selected GPIO.
Using the SDI pin for direct modulation
In this case the MCU has to form the packet and provide the data bits with the right bit timing to the SDI pin.
Using an internal PN9 random data generator
This is a test mode that can be used to measure the shape of the modulated output spectrum.
12 | Rev. 0.7 |
AN415
In the current example, the FIFO is the source of the modulation and the TX packet handler is used to form and transmit the packet, the Modulation Mode Control2 register is set accordingly:
//enable FIFO mode and GFSK modulation
SpiWriteRegister(0x71, 0x63);//write 0x63 to the Modulation Mode Control 2 register
If antenna diversity is used, the correct GPIO configuration must be selected. For the Si4432-T-B1-A-xxx Testcard, use the following configuration for the RF switch:
#ifdef ANTENNA_DIVERSITY
SpiWriteRegister(0x0C, 0x17); //write 0x17 to the GPIO1 Configuration(set the Antenna 1 Switch used for antenna diversity )
SpiWriteRegister(0x0D, 0x18); //write 0x18 to the GPIO2 Configuration(set the Antenna 2 Switch used for antenna diversity )
#endif
#ifdef ANTENNA_DIVERSITY
//enable the antenna diversity mode
SpiWriteRegister(0x08, 0x80); //write 0x80 to the Operating Function Control 2 register
#endif
For the Single Antenna with RF Switch Testcard, use the following configuration for GPIO1 and GPIO2 to control the RF switch:
#ifdef ONE_SMA_WITH_RF_SWITCH
SpiWriteRegister(0x0C, 0x12);//write 0x12 to the GPIO1 Configuration(set the TX state) SpiWriteRegister(0x0D, 0x15);//write 0x15 to the GPIO2 Configuration(set the RX state)
#endif
3.1.4. Select Modulation
EZRadioPRO supports three different modulation types:
Frequency shift keying (FSK)
Gaussian frequency shift keying (GFSK)
On-off keying (OOK)
This example uses GFSK modulation, but the following sections provide an overview of the different modulation types.
Note: The EZRadioPRO devices can be set to provide an unmodulated carrier signal for test purposes by setting the “modtyp[1:0]” bits to 0 (bit[1:0] in the Modulation mode Control2 register).
3.1.4.1. Frequency Shift Keying
FSK modulation uses a change in the frequency of the signal to transmit digital data.
Without modulation, the radio transmits a continuous wave signal (called the CW signal) on the center frequency.
To send a 0 bit, the CW signal is decreased in frequency by an amount equal to the deviation, resulting in a
frequency of f0 fFSK , where f0 is the center frequency and fFSK is the deviation.
To send a 1 bit, the CW signal is increased in frequency by an amount equal to the deviation, resulting in a frequency of f0 fFSK .
Rev. 0.7 | 13 |
AN415
Pout [dBm]
deviation deviation
frequency [Mhz]
f0 - ∆fFSK | f0 | f0 + ∆fFSK |
Figure 4. FSK Modulation
To enable FSK modulation, the “modtyp[1:0]” bits in the Modulation Mode Control2 register are set to 0x2.
FSK modulation is robust against interferers; however, the performance depends on the accuracy of the frequency reference and thus on the crystal used with the radio.
A crystal of 10–20 ppm accuracy is recommended.
Crystals with looser tolerances can be used but require an increase in TX deviation and receiver bandwidth to ensure that signal energy falls within the receiver’s filter bandwidth. Increasing the signal bandwidth results in a decrease in system sensitivity.
3.1.4.2. Gaussian Frequency Shift Keying
GFSK modulation works like FSK modulation except that the data bits are filtered with a Gaussian filter. This filtering reduces the sharp edges of the TX bits resulting in reduced spectral spreading and a narrower occupied bandwidth.
Figure 5. FSK and GFSK Modulation Differences (Time Domain and Spectrum)
GFSK modulation is enabled by setting the “modtyp[1:0]” bits in the Modulation Mode Control2 register to 0x3.
GFSK modulation offers robust link performance providing the highest performance in the narrowest occupied bandwidth. Like FSK, the radio performance and link parameters are dependent on the selected crystal or TCXO.
14 | Rev. 0.7 |
AN415
3.1.4.3. On-Off Keying
OOK modulation encodes the data by switching on and off the power amplifier:
When no data is present, the power amplifier is switched off.
To send a 0 bit, the power amplifier is switched off during the bit period.
To send a 1 bit, the power amplifier is switched on during the bit period.
OOK modulation is enabled by setting the”modtyp[1:0]” bits in the Modulation Mode Control2 register to 0x1.
OOK modulation consumes less current compared to FSK and GFSK modulation since the power amplifier is switched off when transmitting a 0. OOK modulation provides less link robustness than FSK or GFSK modulation and requires more frequency bandwidth. As a result, OOK modulation is normally only used if compatibility with an existing product is required.
3.1.5. Registers Configuration for Si4432 Revision V2
The Si4432 Revision V2 requires some registers to be programmed to values other than their default values: The PLL and VCO must be programmed to the following settings:
/*set the non-default Si4432 registers*/
//set VCO and PLL | |
SpiWriteRegister(0x5A, 0x7F); | //write 0x7F to the VCO Current Trimming register |
SpiWriteRegister(0x59, 0x40); | //write 0x40 to the Divider Current Trimming register |
Note: These settings are not required for subsequent versions of the radio
3.1.6. Registers Configuration for Si4431 Revision A0
The Si4431 revision A0 requires some registers to be programmed to values other than their default value. The PLL and VCO must be programmed to the following values to get optimal current consumption:
//set VCO and PLL
SpiWriteRegister(0x57, 0x01);//write 0x01 to the Chargepump Test register SpiWriteRegister(0x59, 0x00);//write 0x00 to the Divider Current Trimming register SpiWriteRegister(0x5A, 0x01); //write 0x01 to the VCO Current Trimming register
Note: These settings are not required for subsequent versions of the radio.
Rev. 0.7 | 15 |
Loading...